MOS solid-state imaging elements have advantages such as the ability to be driven by a single low-voltage power source and the ability to reduce design costs. Moreover, the fabrication process of MOS solid-state imaging element is similar to the fabrication process of MOS element. Therefore, it is possible to construct system LSI which includes various signal processing circuits (such as logic circuits) using MOS elements, and MOS solid-state imaging devices simultaneously mounted on one substrate.
Generally, a diffusion layer for a source or a drain of a MOS transistor to be used in a logic circuit tends to become shallower in response to requirements for reduction in film thickness and size along with scaling of a power-source voltage. When MOS transistors are miniaturized in a logic circuit, elements of MOS solid-state imaging device also need to be miniaturized.
Meanwhile, instead of conventional Local Oxidation of Silicon (LOCOS) isolation, trench isolation is used as an element isolation structure for MOS solid-state imaging device for the purpose of downsizing the circuit.
FIG. 1 schematically shows a cross-sectional structure of partial extraction (equivalent to an area including two unit cells adjacent in a horizontal direction) of the CMOS image sensor.
In the CMOS image sensor, a plurality of unit cells are formed on a p-type semiconductor substrate (normally a silicon substrate) 31, for example. Each unit cell includes a photoelectric conversion accumulator unit 32 and a scanning circuit unit, which are mutually isolated by a trench isolation region 36.
In the photoelectric conversion accumulator unit 32, a photodiode is formed from a pn junction of the p-type silicon substrate 31 and an n-type diffusion layer 37 formed on a surface thereof.
The scanning circuit unit includes an amplification transistor 33, a vertical address transistor 34 and a reset transistor 35 each of which is made of an NMOS transistor, a signal readout gate 38, an amplification gate 39, a vertical address gate 40, and a reset gate 41. Reference numeral 42 denotes a drain line; reference numeral 43 denotes a signal line; reference numeral 44 denotes a light-shielding film and a connecting line using aluminum, for example; reference numeral 45 denotes an interlayer film; and reference numeral 46 denotes a condenser lens. Illustration of a gate insulating film, a color filter and the like is omitted herein.
In the CMOS image sensor, incident light is subjected to photoelectric conversion inside the semiconductor substrate 31. Accordingly, if the photoelectric conversion accumulator unit 32 is made shallow to accommodate scaling, then performance is deteriorated in relation to the wavelength of the incident light. Therefore, in the CMOS image sensor including the deep diffusion layer 37 for the photodiode, adoption of a trench isolation structure equivalent to a structure for a logic circuit on the same chip incurs problems in inter-pixel isolation or color mixture.
Moreover, although the trench isolation structure can be downsized in comparison with conventional LOCOS isolation structure, it is well known that the trench isolation structure frequently causes defects and damages the semiconductor substrate in the vicinity of trenches because of large stress attributable to processes thereof. Such defects and damages incur an increase in leakage currents, thus causing white spots or dark noises in the CMOS image sensor.
As described above, in the conventional CMOS image sensor, there has been a problem of increased white spots and dark noise attributes to leakage currents caused by deterioration in performances of inter-pixel isolation and color mixture when the trench isolation structure similar to that for the logic circuit on the same chip is adopted.